The present invention relates to an operation of a flash memory device including a multi-level cell (MLC) and, more particularly, to a method of operating a flash memory device with high reliability in reading programmed data.
A NAND flash memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines extending along rows, a plurality of bit lines extending along columns, and a plurality of cell strings corresponding to the bit lines.
The row decoder connected to a string select line, word lines, and a common source line is disposed on one side of the memory cell array. The page buffer connected to the plurality of bit lines is disposed on the other side of the memory cell array.
In recent years, to further increase the integration level of this flash memory, active research has been done on a multi-bit cell that is able to store a plurality of data in one memory cell. This type of a memory cell is called a MLC. A single bit memory cell is called a single level cell (SLC).
A MLC capable of storing 4-bit or 8-bit data information has recently been developed out of 2-bit data information. Technologies for improving operational reliability of a chip are required to address abnormal conditions that occur during MLC chip operation (for example, power-off due to the consumption of a battery).